The invention is related to the field of Electronic Design Automation, and more specifically, to a method of reducing pessimism in static timing analysis when considering variation effects on the circuit delay.
Static timing is used widely in order to verify the timing of digital integrated circuit designs by calculating delays and propagating signal arrival times to determine the interval in which signals will be stable within a single clock cycle. In particular, for internal storage elements, the latest (earliest) arrival time data propagated along a data path is compared against the earliest (latest) arrival time propagated along a clock path to identify potential setup (hold) violations. The difference between the data and clock path arrival times, including the setup or hold time of the sequential element is referred to as ‘slack.’ This difference is computed so that a negative slack value signals a timing violation. For a setup constraint, if the minimum (or early) clock arrival time minus the maximum (or late) data arrival time is negative, the data may still become unstable following the occurrence of a clock transition, thus preventing the correct data from being stored in the storage element. Similarly, for a hold constraint, if the minimum (or early) data arrival time minus the maximum (or late) clock arrival time is negative, the data may still become unstable before the occurrence of a clock transition, again preventing the correct data from being stored in the storage element. The comparison of two timing values (generally early and late) converging at a circuit element (e.g., a latch) is referred to as a timing test.
Circuit delays may be affected by a wide variety of parameters, broadly categorized as either manufacturing (either front or back end of line), environmental (e.g., voltage, temperature), reliability (e.g., transistor performance degradation over product lifetime), or model uncertainty (e.g., on a cell-type basis). As critical process dimensions continue to shrink, timing variability increases as a fraction of the overall design cycle time. In addition, new technology features, such as the ability to independently scale voltages for different subsections of the design for power management purposes, increase the number of independent parameters that need to be considered to achieve an accurate timing analysis. Also, the increase in the fraction of wire delay along critical paths makes the variability of each metal layer essential to consider.
In general, it is not possible to determine a priori which combination of parameter settings will produce the most critical timing. Furthermore, delays may not be monotonic in all parameters, so that for different paths across a chip, different parameter assignments may be required to generate the latest (earliest) possible path delays. For example, when considering variability in wire thickness, it is assumed that thin wires generally create the latest arrival time for wire-delay dominated paths due to increased wire resistance, whereas paths which are gate-delay dominated will typically exhibit longer delays when thick wiring is considered, due to increased wire capacitance loading of gates.
Existing design automation tools and methodologies require an exhaustive search of all possible parameter combinations in order to guarantee a true worst-case coverage. However, given the increasing number of independent parameters that have a significant impact on delay, such an approach is fast becoming impractical.
One alternative to this exhaustive analysis is to bound the problem by computing late delays/arrival times assuming the slowest possible conditions, and simultaneously assuming the fastest conditions for early delays/arrival times. This is called a “bounding method” or a “bounded timing analysis, and the early and late delays and the parameters used in their computation within the analysis are called “bounded” values. While this guarantees worst-case coverage (i.e., that all potential timing errors will be detected) without the need for multiple analyses, such an approach typically leads to overly pessimistic results since correlation is not properly accounted for. By way of example, for internal timing constraints, it can easily lead to comparing a late mode data path which assumes, for instance, a low supply voltage, against an early mode clock path where a high supply voltage was assumed. If the design only contains a single power supply source, the assumption is deemed to be inconsistent and pessimistic since the circuits cannot operate simultaneously at two different power supply voltages (Note: this example ignores across-chip IR drop effects.) The over-conservative nature of bounding techniques often precludes their practical use, forcing circuit designers to explicitly perform multiple analyses as described above.
In the special case where the clock and data paths share common circuits, a method of removing the common path pessimism is described in U.S. Pat. No. 5,636,372 to D. J. Hathaway et al., “Network timing analysis method which eliminates timing variations between signals traversing a common circuit path,” which reduces the pessimism of the bounding method by tracing the paths contributing to a failing test, i.e., one having a negative slack, and adding to that slack the difference between the bounding early and late mode delays of cells in the common portion of the path. However, the method described cannot remove pessimism due to paths that do not physically share the same cells, but which are dependent on the same underlying varying parameters.